Nonvolatile memory devices have become increasingly popular, especially flash memory devices. FIG. 1 shows a conventional flash memory cell. The flash memory cell has source and drain regions 2 and 3, respectively, formed in a P-type semiconductor substrate 1 (or bulk), a floating gate 6 formed over a channel region 5 and between the source and drain regions 2 and 3, respectively. A thin (100 .ANG.) insulator 4 is interposed between the floating gate 6 and the substrate 1. A control gate 8 is formed over the floating gate 6 with a second insulator 7 interposed therebetween. The control gate 8 is coupled to a word line.
Table 1 shows the conventional approach to programming, reading, erasing, and erase-verifying the flash memory cell shown in FIG. 1.
TABLE 1 PROGRAM READ ERASE VERIFY Vg +5V +10V -10V +3V Vd +1V +5V FLOAT +5V Vs GROUND GROUND FLOAT GROUND Vb GROUND GROUND +6V to +9V GROUND
The flash memory cell is programmed by applying a ground (0V) to the source 2 and the bulk 1, a high voltage of +10V to the control gate 8, and a positive voltage of +5V to the drain 3 resulting in appropriate hot electron generation. The above-described voltages cause a sufficient amount of negative charges to accumulate in the floating gate 6 creating a (-) potential. The (-) potential forces a threshold voltage of the flash memory cell to be increased during reading.
During a read operation, a voltage of +5V is applied to the control gate 8 and the ground voltage is applied to the source 3. Under these conditions, the channel of the programmed memory cell is nonconductive. That is, no current flows from the drain 3 to the source 2 via the channel 5. At this time, the programmed memory is in an off state, and its threshold voltage, as illustrated in FIG. 2, is distributed within about +7V to +9V.
Flash memory cells in a sector are simultaneously erased by means of the so-called Fowler-Nordheim (F-N) tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage of about -10V is applied to the control gate 8 of each memory cell transistor and a positive voltage between about +6V to +9V--suitable to make the F-N tunneling--is applied to the substrate 1. Under this bias condition, the drain and source 2 and 3, respectively, of each cell are maintained at a floating state as shown in Table 1. This erase scheme is termed Negative Gate and Bulk Erase (NGBE). A strong electric field between 6 to 7 MV/cm is generated between the control gate 8 and the bulk 1 under the above-described bias condition, so that negative charges accumulated in the floating gate 6 are discharged into the source 2 through the thin insulator 5. The negative charges force a reduction in the threshold voltage of the memory cell during reading.
The particulars of various bulk erase methods associated with a flash memory device are disclosed in U.S. Pat. No. 5,781,477 entitled "FLASH MEMORY SYSTEM HAVING FAST ERASE OPERATION", U.S. Pat. No. 5,132,935 entitled "ERASURE OF EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLS", U.S. Pat. No. 5,220,533 entitled "METHOD AND APPARATUS FOR PREVENTING ERVERERASURE IN A FLASH CELL", U.S. Pat. No. 5,513,193 entitled "NON-VOLATITLE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CHECKING THE THRESHOLD VALUE OF MEMORY CELLS", and U.S. Pat. No. 5,805,501 entitled "FLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGIC", incorporated herein by reference.
After performing the above-described NBGE operation, an erase verification operation is performed to check whether a threshold voltage of each flash memory cell in the sector exists in a target threshold voltage range corresponding to the on state (e.g., +1V to +3V). During the erase verification operation, as shown in Table 1, an erase verification voltage of about +3V is applied to the control gate 8, a voltage of about +5V to the drain 3, and the ground voltage (0V) to the source 2 and the bulk 1.
Typically, the threshold voltage of the erased memory cell is distributed in a range of +1V to +3V. However, when all of the memory cells in the sector are simultaneously erased, a threshold voltage of one or more flash memory cells can be lowered below +1V. When this happens the flash memory cell is termed an over-erased cell. The over-erased cell can be cured by an erase repair operation that shifts the threshold voltage of the over-erased cell back to a target threshold voltage range of the on cell (e.g., +1V to +3V).
The erase repair operation is carried out by applying the ground voltage (0V) to the source 2 and the bulk 1 of the over-erased cell, a voltage of about +3V to the control gate 8, and a voltage of about +5V the drain 3. This bias condition accumulates charges in the floating gate 6 of an amount less than those accumulated during a program operation. The erase repair operation, as illustrated in FIG. 2, results in the threshold voltage of the over-erased memory cell shifting back into the target threshold voltage distribution (e.g., +1V to +3V).
One problem associated with the above-described erase method is the length of time that it takes to perform the additional erase repair operation. This is because the repair operation increases the overall time it takes to erase the memory cell. As well known to those skilled in the art, such a problem arises when excess electric field is applied across the floating gate of the flash memory cell.
Applying a weaker electric field can lower the time it takes to perform an NGBE erase operation. The overall erase time, however, remains unchanged because while applying a weaker electric field results in none to fewer over-erased cells, eliminating the time required to perform the over-erase repair operation, the actual erase operation takes longer.